Celeron

The Celeron began as a scaled down version of the Pentium II and was designed to compete against similar offerings from Intel’s competitors. The Klamath-based Covington core ran at 266 and 300 MHz and were constructed without an L2 cache. However, adverse market reaction saw the Deschutes-based Mendocino core introduced with an 128 Kb L2 cache and ran at 300, 333, 400, 433, 466, 500 and 533 MHz. Celerons have the same L1 cache as their bigger brothers—Pentium II and III. The important distinction is that the L2 cache operates at full CPU clock rates, unlike the Pentium II and the SECC packaged Pentium III. (Later variants of the Pentium III had an on-die L2 cache which ran at full CPU clock rate. The Celeron III (Coppermine128 core)has the same internal features as the Pentium III, but has reduced functionality: 66 Mhz clock rate, no error correction codes for the data bus, and parity creation for the address bus, and a maximum of 4 GB of  address space. Celeron III Coppermine128s with a 1.6 V core and a 100 MHz were produced in 2001 and operated at core speeds of up to 1.1 Mhz. Tualatin-core Celerons were put on the market in late 2001 and ran at 1.2 GHz. 2002 saw the final versions produced running aty 1.3 and 1.4 MHz.